 ---------------------------------------------------------------------------------
  -- Design Name : Branch Calculator
  -- File Name   : IdBranchCalc.vhd
  -- Function    : Checks for branch operations
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity IdBranchCalc is
  port (
    enable:   in  std_logic;
    opH:      in  std_logic_vector(2 downto 0); --vishih 3b opCode
    in1:      in  word32;
    in2:      in  word32;
    br_cnd:   out std_logic := '0'
  );
end entity;

architecture behavioral of IdBranchCalc is
signal gr,eq,lo:   std_logic;

begin
  cmp: GenCmp32 port map(enable,in1,in2,gr,eq,lo);  
    
  process(all)
  begin
    br_cnd <= '0';
    
    if(enable = '1') then
      case opH is
        when OPC_BEQ(5 downto 3) =>
            br_cnd <= eq;

        when OPC_BNQ(5 downto 3) =>
            br_cnd <= not eq;

        when OPC_BLT(5 downto 3) =>
            br_cnd <= lo;

        when OPC_BGT(5 downto 3) =>
            br_cnd <= gr;

        when OPC_BLE(5 downto 3) =>
            br_cnd <= lo or eq;

        when OPC_BGE(5 downto 3) =>
            br_cnd <= gr or eq;

        when others =>
            br_cnd <= '0';
      end case;
    end if;
  end process;

end architecture behavioral;